1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, more specifically, a floating-gate tunnel-injection type electrically-erasable programmable read-only-memory device (EEPROM).
2. Description of the Prior Art
Semiconductor read only memories (ROM's) include mask ROM's and programmable ROM's (PROM's). Some PROM's are of the fuse type or diode junction breakage type in which information cannot be erased and rewritten after once being written, while others are of the erasable type (EPROM) in which information can be erased, for example, by ultraviolet rays and rewritten even after once being written.
Recently, EEPROM's have been developed. In EEPROM's, written information can be erased by electricity. EEPROM's include metal nitride oxide semiconductors (MNOS's), described in, for example, IEEE, "International Solid-state Circuit Conference WAM 3.6", 1976, Hagiwara T. et al, and floating-gate tunnel-injection type EEPROM's, described in, for example, "Electronics", McGraw-Hill Co., Feb. 28, 1980, pp. 113 to 117.
A floating-gate tunnel-injection type EEPROM has a structure similar to that of a metal oxide semiconductor (MOS) transistor, comprising a source, a drain, and a gate, but has above the gate which is floating a second gate and an extremely thin insulating layer for tunneling inserted between the floating gate and the drain. The thickness of the tunneling insulating layer is, for example, about 10 to 15 nm.
In this type of EEPROM, writing and erasing is effected by tunnel injection and discharge between the drain in the substrate and the floating gate through the tunneling insulating layer. Reading is effected by detecting conduction or nonconduction between the source and the drain according to presence or absence of charges in the floating gate.
The tunneling insulating layer must be both very thin and of a high quality. Formation of such a tunneling insulating layer, however, is difficult since the previous ion implantation used in the formation of the drain region in the substrate damages the surface of the substrate.
In another area, a floating-gate tunnel-injection type EEPROM has been proposed wherein the width of the overlap of the drain diffusion region and floating gate straddling a gate insulating layer is made smaller than the depth of the drain diffusion region so as to allow operation by less than rated power sources (see Japanese Unexamined Patent Publication (Kokai) No. 57-91560). In this EEPROM, the portion of the drain diffusion region just below the floating gate is formed by diffusing a dopant transversely from an outwardly neighboring region.
This EEPROM does not operate very well, however, since the edge of the drain diffusion region exists just below a very thin tunneling insulating layer. Though application of a high voltage between the floating gate and the drain diffusion region is preferable for tunnel injection and discharge therebetween, such a high voltage will cause junction breakdown of a pn junction when the insulating layer just over the edge of the junction is too thin.